Welcome

Welcome to the homepage of svjson project!

The project introduces JSON decoder and encoder in pure SystemVerilog without any external dependencies.

  • JSON decoder can parse values from string or file

  • JSON encoder can dump values to string or file

  • JSON values (object, array, string, number, bool) are represented with collection of wrapper classes

  • JSON encoding capability can be added to user classes with collection of interface classes

  • Additional classes for encoding SystemVerilog enums and bit vectors of any width

  • Error reporting and propagation system inspired by Rust

Implementation follows ECMA standard with some limitations:

  • \b and \u escape sequences are not supported for decoder/encoder

  • Nesting depth is limited for decoder (1024 by default, limit is controllable)

  • No recursion detection for encoder

Supported EDA

The project’s code is provided as a SystemVerilog package. Various EDA tools have different level of SV support, so below is a summary table.

Supported EDA tools

Tool

Lint

Test

CI

Verilator 5.24

✅

✅

✅

Synopsys VCS

✅

✅

❌

Cadence Xcelium

✅

✅

❌

Siemens Modelsim

✅

✅

✅

Siemens Questa

❌

❌

❌

  • Lint - the package is compilable without warnings using this tool

  • Test - the package is tested using this tool via SVUnit

  • CI - this tool is used in CI to perform automatic checks

Extending support of other simulators is planned, but Verilator is the main simulator for project as it is the only viable option to organize CI and opensource flow.

How to setup and compile the code?

Please refer to User Guide: Integration section.

How to parse JSON file or string?

Please refer to User Guide: JSON Decoder section.

How to dump JSON file or string?

Please refer to User Guide: JSON Encoder section.

Where complete API is described?

Please refer to Class Reference Manual.

How to contribute, run tests, etc.?

Please refer to Developer Guide.

What has changed for version x.y.z?

Please refer to Changelog.

Are there any alternatives?

DVCon US 2018, IEEE-Compatible UVM Reference Implementation and Verification Components: Objects and Policies, Mark Peryer.

Slides

Slides contain references to a JSON uvm_printer with some code.

SNUG 2013, Applications of Custom UVM Report Servers, Gordon Mc Gregor

Artice, sources

Article mentions JSON implementation of UVM server, however, link to the code doesn’t work.

UVM Tutorial for Candy Lovers – 33. Defining do_print

Link

Famous UVM tutorial shows how to implement simple JSON uvm_printer with code.

JSON.sv

Github

Implementation of JSON encoder/decoder in SystemVerilog. Integrated into FuseSoc ecosystem. It has only few tests and almost no documentation.

JSONPacketParser

Github

Project uses the JSMN library to parse a JSON file into a C data structure. This data structure is then passed to a SystemVerilog testbench via DPI.

JSONinSV

Github

JSON encoder and decoder in SystemVerilog. It is well tested (own framework is introduced). Project comes with a nicely structured README (on Chinese, though).

JSON-for-VHDL

Github

JSON decoder in VHDL. Tested against well-known JSON Test Suite.